A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems

This paper presents a comprehensive analysis of mismatch-insensitive clock generation techniques for general parallel sampled-data systems. Two jitter-insensitive clock generation schemes are described, a class of multi-purpose, low-jitter, multi-phase clock generator platform is proposed. The platform can provide clock phases for the two pre-described clock generation schemes and has the advantages of being insensitive to timing mismatches, having a simple and highly robust architecture such that the clock generator can be generalized not only for an arbitrary number N of time-interleaved (TI) paths, but also can be applied to general TI sampled data systems including ADCs, DACs and N-path filters.