Reconfigurable HPC: torpedoed by deficits in education?

Currently there is a deep chasm between reconfigurable computing (RC) and the way, how "classical" CS people look at parallelism (Hartenstein, 2004). In education until recently RC has been subject of embedded systems or SoC design within EE departments, whereas most classical CS departments have ignored the enormous speed-up opportunities which can be obtained from this field. Only a few departments provide special courses mostly attended by a small percentage of graduate students. Conferences like ISCA stubbornly refused to include RC and related areas in their scope. Also many major players in the IT market have mainly ignored this area. Since some months ago this situation is on the way to be changed. An increasing number of colleagues from classical parallel computing or supercomputing communities is going to be ready to discuss fundamental issues. A major break-through also in CS education is overdue. Not only the HPC community urgently needs to benefit from a curricular revision. A rapidly increasing percentage of programmers implements code for embedded systems. However, most CS graduates are not qualified for this changing labour market. With their procedural-only mind set they cannot cope with hardware/configware/software partitioning. Currently such tasks are mainly carried out by EE professionals. In order not to lose this competition, and, to avoid a disaster for future CS graduates looking for their first job, CS departments have to wake up.