A methodology for accurate assessment of soft-broken gate oxide leakage and the reliability of VLSI circuits

We present a comprehensive methodology for modeling, as a function of time, increased standby leakage current of VLSI circuits due to soft-breakdown. Predictions, using a post-soft-breakdown leakage-scaling model and device-level time-dependent dielectric breakdown (TDDB) data, agree remarkably well with observations of circuit leakage. The implications of this predictive model for the leakage current regarding the appropriate evaluation of the absolute reliability of intrinsic, ultra-thin oxides are discussed.