Contention-induced latchup

Traditional external latchup trigger mechanisms include transmission line reflections which create large overshoot or undershoot voltages, power supply sequencing of multiple supplies, or discharge of charged cables or human discharges on cables or connectors. This case study will demonstrate the interaction between I/O circuit design, card design, and test structure design which combined to create a card-level latchup failure at typical use conditions. In this investigation of a failing 0.18/spl mu/m non-epitaxial CMOS ASIC chip, a new latchup trigger mechanism is identified. This contention-induced latchup involved IEEE 1149.1 boundary scan structures for open-drain drivers which produce transient driver contention during JTAG testing on an unused, dotted, I/sup 2/C bus whose off chip drivers employed a Miller feedback capacitor in the I/sup 2/C driver output stage. Ironically, the common occurrence of tying off four unused I/sup 2/C drivers on a standard product was the initial factor which contributed to the card-level latchup failure. This paper also examines the domino behavior of latchup as it spreads from the initial trigger device to adjacent transistors as illustrated by the failing chip behavior at the tester and the physical failure analysis.