On the design of hybrid DRAM/SRAM memory schemes for fast packet buffers

We address the design of a packet buffer for future high-speed routers that support line rates as high as OC-3072 (160 Gb/s), and a high number of ports and service classes. We describe a general design for hybrid DRAM/SRAM packet buffers that exploits the bank organization of DRAM. This general scheme includes some designs previously proposed as particular cases. Based on this general scheme, we propose a new scheme that randomly chooses a DRAM memory bank for every transfer between SRAM and DRAM. The numerical results show that this scheme would require an SRAM size almost an order of magnitude lower than previously proposed schemes without the problem of memory fragmentation.