A clock jitter insensitive multibit DAC architecture for high-performance low-power continuous-time /spl Sigma//spl Delta/ modulators

The design of a clock-jitter insensitive multibit digital-to-analog converter (DAC) topology for high-performance low-power continuous-time /spl Sigma//spl Delta/ modulators is presented. The 9 level DAC circuit uses a time-variant feedback pulse shape to reduce both the clock jitter influence as well as the slew rate and bandwidth requirements of the used amplifiers and therewith the overall power consumption of the modulator. Additional it will be shown that the proposed concept is suitable for very low supply voltages. The DAC architecture was exemplary implemented in a second-order 2MHz CT /spl Sigma//spl Delta/ modulator for UMTS applications operating at a sample frequency of 50MHz. The modulator operates from a single 1.8V power supply and achieves a 11-bit dynamic range for the 2MHz passband.