Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment

In this paper, we investigate the effectiveness of simultaneous multiple supply and threshold voltage assignment in minimizing the total power (static+dynamic) in generic digital CMOS designs. Achievable power reductions under varying conditions are investigated, including static-power limited designs and sub-1-V processes. Rules-of-thumb are developed for optimal V/sub dd/'s and V/sub th/'s to be used in future designs. These models show the optimal second V/sub dd/ to be approximately half the nominal V/sub dd/ while the potential total power savings is significantly greater than previously anticipated (60%-65%). We describe the impact of level conversion delays and also demonstrate that the scaling properties of multivoltage systems are very good, particularly when considering impending device scaling advancements.