2D analysis of bottom gate misalignment and process tolerant for sub-100 nm symmetric double-gate MOSFETs

The effects of bottom gate misalignment in symmetric double-gate MOSFETs are examined in this paper. Higher off-current and subthreshold swing is observed due to punchthrough at the bottom interface with bottom-gate misalignment. In addition, on-current reduction is also observed. The allowable bottom gate misalignment of very-deep-submicron devices due to process variation is studied, indicating the tighter process control required in the use of DG MOSFET compared with single-gate MOSFETs.