Evaluation of network topologies for a run time re-routable network on a programmable chip

Networks on a chip have become a popular way to integrate IP cores. In the field programmable logic domain there is the added possibility that IP cores can be added and removed from the chip using run time reconfiguration. The widely advocated fixed mesh packet forwarding network topology, where the cores are placed in fixed sized tiles created by the mesh, may lead to area fragmentation when the cores and the tiles are not exactly the same size. An alternative is to allow variable sized cores to be placed in any free location and to re-route the network to connect to them. We report here on a study that re-evaluates the classic network topologies against criteria that reflect an FPGA environment were the network might be rerouted as each new core is placed or removed from the FPGA. The most promising network configuration, a set of star connected tristate busses with token ring arbitration, (which we call a RingBuss) has been implemented. Its performance and area overheads are compatible with applications suitable for one million gate equivalent FPGAs.