Using a distributed rectangle bin-packing approach for core-based SoC test scheduling with power constraints

We present a new algorithm to co-optimize test scheduling and wrapper design under power constraints for core-based SoCs (System on Chip). Core testing solutions are generated as a set of wrapper designs, each represented by a rectangle with width equal to the test time and height equal to the number of TAM (Test Access Mechanism) wires used. The test-scheduling problem with power constraints is formulated as the distributed rectangle bin-packing problem, which allows wrapper pins to be assigned to non-consecutive SoC pins. The generalized problem for multiple-TAMs is solved by global optimization using evolutionary strategy and the sequence-pair representation. Experiments on ITC'02 benchmarks are very encouraging.