Instruction set architecture of the determined memory access processor

There are lot of applications that demand intensive data streams processing in real time nowadays. These tasks are usually performed by dedicated or algorithm-specific computer systems. Such systems design is quite complicated and laborious process while time-to-market is critical. So there is a need for the computer-aided dedicated systems design methods development. In given work instruction set architecture of the determined memory access processor is proposed. Such a processor usage will grant very short terms of application-specific systems design.