A CAD methodology for the characterization of wide on-chip buses

In this paper, we describe a CAD methodology for the full electrical characterization of high-performance, on-chip data buses. The goal of this methodology is to allow the accurate modeling and analysis of wide, on-chip data buses as early as possible in the design cycle. The modeling is based on a manufacturing (rather than design-manual) description of the back-end-of-the-line (BEOL) cross section of a given technology and on a full yet contained description of the power-ground mesh in which the data-bus is embedded. One major aspect of the resulting electrical models is that they allow the designer to evaluate the wide bus from the three viewpoints of signal timing, crosstalk (both inductive and capacitive), and common-mode signal integrity. Another major aspect is that they take into account such important high-frequency phenomena as the dependence of the current return-path resistance on frequencies. The CAD methodology described in this paper has been extensively correlated with on-chip hardware measurements.