A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

A 0.622-8 Gb/s CDR circuit using injection locking for jitter suppression and phase interpolation in high bandwidth SOC solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection MUX. For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2 V 0.13 /spl mu/m CMOS CDR consumes 33 mW at 8 Gb/s. Die area, including voltage regulator, is 0.08 mm/sup 2/. Recovered clock jitter is 6.9 ps rms/49.3 ps peak-to-peak at a 200 ppm bitrate offset.