Design & implementation of all digital I-Q modulator and demodulator for high speed WLAN in FPGA

The project aims to provide the front-end digital signal processing functions in a quadrature modem for IEEE 802.11a WLAN test-bed. The design and implementation of a pair of all digital I-Q modulator and demodulator suitable for high-speed wireless communication is discussed. The effects of finite bit resolution are considered in the implementation of both modulator and demodulator. Each of them is integrated with 40-tap FIR square root raised cosine filter with excess bandwidth 0.15. There are several issues that needed to be considered in the real implementation in FPGA to achieve the goal of a real time implementation. The system clock needs to run at least 80 MHz to perform real time signal processing. Both modulator and demodulator utilize a total of 120 K FPGA equivalent gates, which is only 2% of available logic of a Xilinx FPGA XC2V-6000. The all-digital modem in FPGA results in a very flexible chipset.