A low-power low-jitter adaptive-bandwidth PLL and clock buffer

A multi-context programmable on-chip communication network is implemented using a matrix of Flash-EEPROM pass-transistor switches (FPT) in a 0.18/spl mu/m technology. The prototype 8-context, 8/spl times/8 64b crossbar includes 576k FPT and >8k bi-directional tristate repeaters in an area of 1.38mm/sup 2/. Based on 2/spl times/2 building blocks, wave pipelining and elastic interconnect, data is transferred at 6.4Gb/s per channel, with independent clocks at both ends.