Automating the device interface board modeling for virtual test

Virtual test (VT), allowing the verification of test programs and associated test hardware in a simulation environment before silicon and without a real automatic test equipment (ATE), has proven to be an effective technique to cut time-to-market and costs for mixed-signal system on chip (SoC), even in an industrial environment. Mixed-signal VT requires behavioral models both for the device under test (DUT) and the device interface board (DIB), interfacing the DUT with the ATE. Test engineers are used to design the DIB circuitry in detail. The resulting schematic is used for the layout and manufacturing of the DIB. In order to develop a behavioral model of the DIB, the test engineer has (1) to abstract this low-level schematic, by identifying the relevant functions and signal flows, and (2) to write the model manually. This bottom-up procedure is very time consuming and may lead to inconsistencies and errors. This paper introduces a new top-down flow for DIB development, allowing the automatic generation of the DIB behavioral model using VHDL as the modeling language. Test engineers enter the design of the DIB by a schematic entry tool at a very abstract level (i.e. as a block diagram). Using specific libraries, test engineers can then generate the real circuit schematic or VHDL model by dedicated netlisters.