A high voltage CMOS ADSL line driver

This paper reports the successful design and implementation of a high voltage ADSL line driver in a conventional submicron CMOS process. The line driver features a total area of 0.2 mm/sup 2/, an output impedance of 0.09 /spl Omega/ and a bandwidth of 3.4 MHz. It can be integrated into a short loop Subscriber Line Interface Circuit (SLIC), supporting ADSL Full Rate applications.