A balanced clock network design algorithm for clock delay, skew, and power optimization with slew rate constraint

A heuristic algorithm for optimized clock network design is presented. The algorithms for optimization of clock skew, delay, and power considering slew rate constraint for a balanced IC clock tree are implemented using a modified method of cautious approach. Algorithms developed are verified with the model of a real chip, i.e. post layout model of an FPGA chip. HSpice simulations at 115/spl deg/C, with CMOS 0.35 /spl mu/m models and parameters show a 60% reduction in the clock slew rate and a 23% improvement in the power dissipation when compared to the results of the initial, unoptimized chip.