A comparison of three multipliers based on the V/sub gs//sup 2/ technique for low-voltage applications

Multipliers are one of the most important building blocks in analog circuits. In this work, three new low-voltage topologies used to implement four-quadrant multipliers based on the V/sub gs//sup 2/ technique are presented and compared. The operation and requirements for the multipliers are described. Theoretical results are verified with HSPICE simulations using a 3.3-V, 0.35-/spl mu/m CMOS process.