BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction

Fast and accurate interconnect parasitic parameter extraction has become increasingly critical for verification and analysis in VLSI. In this paper, a fast hierarchical extraction approach based on the boundary element method (BEM) is presented for 3D parasitic capacitance computation. Hierarchical partition of the 3D field creates many parts which are called 3D BEM blocks. After combining all the 3D BEM blocks, the capacitance matrix for a given set of nets can be computed by applying the boundary conditions. Numerical results shows that this method performs many times faster than the 3D field solver, with equal accuracy.