A method of implementing bit-serial LDI ladder filters in FPGAs using JBits

A simulated annealing design method for low hardware cost bit-serial Lossless Discrete Integrator (LDI) recursive digital filter implementations using Field Programmable Gate Arrays (FPGAs) with JBits/spl trade/ is presented. This method jointly minimizes the magnitude frequency response error and the filter hardware cost. The next-neighbor connectivity of bit-serial systems is exploited to create a placement method using JBits/spl trade/ to avoid time-consuming general-purpose placement tools for FPGAs in addition to the hardware cost reduction benefits of bit-serial architectures. A design example using the proposed method is presented in which a 30.2 percent hardware cost reduction is obtained.