A fourth-order cascaded sigma-delta modulator with DAC error cancellation technique

An architecture that improves the performance degradation caused by the DAC nonlinearity in a cascaded multibit sigma-delta modulator is presented. The proposed architecture, with an extra feedback path in each internal stage, can totally cancel out the errors caused by the DAC nonlinearity at the final stage and, in general, increases the shaping function of DAC errors by one order for the other internal stages as compared to the MASH structure. Behavioral simulation shows that the proposed fourth-order modulator has excellent immunity of DAC nonlinearity over the MASH structure when OSR is greater than 16. With maximum DAC integral nonlinearity (INL) of /spl plusmn/0.05 LSB and an OSR of 32, an improvement of 15 dB over the MASH structure has been observed.