Configurable architecture for smart pixel research

The microprocessor industry has been striving hard to keep pace with Moore's law. Two of the principal problems have been the interconnect delay and wiring density. This paper presents a new and efficient design, implementation of an array of single bit optical RISC processors, which demonstrates the distribution of data through integrated CMOS photodetector and photoreceiver circuit. The CASPR chip incorporates an Instruction Fetch Unit (IFU) to fetch the instructions from a host computer. The Processing Element uses the stream of instructions to perform the necessary calculations. The IFU determines the branching of the instruction and gives the instructions in the correct sequence to the Processing Element. Each Processing Element (PE) consists of its Control Unit, Data path, ALU and Memory Register Bank. Communication between the PEs is effected by using nearest neighbor communication. The principal advantage of our design is that the user can decide what applications the chip needs to be used for and how. The final chip would comprise of a 4 /spl times/ 4 array of PEs with a single IFU interfacing with the host computer.