System-level power evaluation of an embedded software data block processing algorithm

Data block processing algorithms have demonstrated significant efficiency in terms of low power consumption when applied to mainly hardware implementation of digital signal processing algorithms. In this paper, a generic data block processing algorithm is applied to the implementation of an FIR filter on a system-on-chip platform incorporating a micro controller and a programmable 32 bit DSP processor. The block processing algorithm is evaluated at the system-level including the performance metrics speed, energy, power and area. The data block processing technique achieves a reduction in energy consumption of 18% and memory accesses are reduced by 44%, for an 8 tap FIR filter. Our algorithm is targeted as a macro block, which can be re-used in the design of more complex DSP systems on the SoC platform.