Reduced instruction set computers

The infulential computer architects believe that conventional microprocessor architectures have reached a performance limit and represent a dead end in processor evolution. A new approach, the Reduced Instruction Set Computer (RISC) has emerged from research laboratories and is poised to enter the marketplace. RISC processors achieve performance by a careful selection and streamlining of the instruction set making possible a high-performance pipelined implementation. But not all microprocessor designers agree with the RISC approach. Panelists will address the future role of RISC and whether it will displace conventional architectures in the next generation. To be debated is whether or not there is a need for a new architecture, even if technically superior, in the existing volume marketplace. Possibly, as technology advancements appear, the mood could change during the next five years.