A 1Mb CMOS DRAM

THIS PAPER WILL DESCRIBE a 1Mb DRAM with a typical RE access time of 80ns. One mode of operation allows a 20Mb/s data rate with relaxed system requirements*. A single 5V supply powers the device, which dissipates 160mW for a 260ns cycle. During standby (RE high), the dissipation is 0.5mW for TTL level inputs. The DRAM is packaged in an 18-pin, 300-mil plastic DIP. A mask option allows the DIP pin out to meet either the proposed JEDEC standard or an evolutionary pattern which is more compatible with the standard 256K DRAM 16-pin package pin out.