A dual processor serial data controller chip

A DUAL PROCESSOR microprogrammable chip that implements a specialized architecture for high-speed serial data controllers will be described. The chip measures 218 mils by 244 mils and contains 22,000 transistors which yields a device density of 0.41 devices per square mil. This device count represents a four-fold increase in chip complexity over an earlier model". The processing capability supported by this chip relieves the system CPU of many of the low-level control tasks associated with controller applications. Operations are specified by the systems CPU and executed independently by the chip. Once an operation has been specified, no system CPU intervention is required