An intermediate representation for behavioral synthesis

An intermediate representation for behavioral and structural designs that is based on annotated state tables is described. It facilitates user control of the synthesis process by allowing specification of partially designed structures, and a mixture of behavior, structure, and user specified bindings between the abstract behavior and the structure. The format's general model allows the capture of synchronous and asynchronous behavior, and permits hierarchical descriptions with concurrency. The format is easily translated to VHDL for simulation at each stage of the design process. It therefore complements a good simulation language (VHDL) by providing an excellent input path for behavioral and register-transfer synthesis. The format's simple and uniform syntax allows it to be used both as an intermediate exchange format for various behavioral synthesis tools, and as a graphical tabular interface for the user, thereby allowing a natural medium for automatic or manual refinement of the design.<
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