A New Chip Carrier for High Performance Applications: Integrated Decoupling Capacitor Chip Carrier (IDCCC)

The impact of inductance has rarely been considered in semiconductor Packaging. This is the reason for using the capacitor in the first place: it is a small, local energy reservoir for those current transients which cannot go back to the power supply without causing unacceptahly large voltage drops (V = L di/dt). Since 1978 a new chip carrier with integrated deeoupling capacitor (IDCCC) has been studied. T]he capacitor is located inside the bottom layer in a threelayer or a single-layer chip-carrier. The ceramic package previous!y used had a nonactive bonding pad layer: with our IDCCC, this layer (standard thickness is 25 mils) is made out of several layers from 3 to 5 mils with the electrodes. The technology is about the same as the one used in multilayer ceramic capacitors. This capacitor is located just under the device, but not under the conductor I/O to avoid a parasitic capacitive coupling. With the coming of leadless and leaded full array chip carriers such as pin grid array, we applied the same concept with a Capacitor inside the cap. The results with different current-pulse signals show the effects of the capacitor's inductance, resistance, and capacitance. The main specifications of this new chip carrier will be presented. In addition to improving speed and electrical Performances, the IDCCC allows an increase in density and in reliability level.