A Multiprocessor Architecture for the (M, L)-Algorithm Suitable for VLSI Implementation

The
(M, L)
-algorithm has been widely used in speech and image encoding. Recently, use of
(M, L)
-Iike algorithms has been suggested for decoding phase codes. With its ever-increasing use, there arises a need to explore architectures suitable for real-time applications. Toward this end, we present a multiprocessor architecture for the
(M, L)
algorithm that employs an SIMD (single instruction-multiple data) machine structure. The considerations involved in interconnection network design are discussed. The main functions of the network controller are switch state selection and synchronization. The number of switching elements required is significantly less than the elements required in the universal permutation network. These features make this architecture suitable for VLSI implementation. The tradeoff between number of processors and encoding time is also discussed.