Transient selection gates using breakdown

A new class of gates suitable for selection in memories is presented. The gate utilizes charge storage and avalanche breakdown to obtain a low power dissipation (~6/spl times/10/SUP -12/ J/selection, or ~60 /spl mu/W/gate in a 10-MHz-repetition selection rate), more than an order of magnitude below that of conventional TTL gates. Only narrow (/spl gsim/ 1 ns), nonoverlapping pulses are needed and external dc voltages are not required. A totally transient mode of operation is described that requires no resistors. Also described are the results of analog simulations using discrete components.