A 32-bit VLSI CPU with 15-MIPS peak performance

A 32-b single-chip VLSI CPU which implements the entire 140 instructions of the Hewlett-Packard precision architecture (HPPA) using direct hardwired decoding and execution is described. A sustained pipeline performance of 10.8 million instructions per second (MIPS), 15-MIPS peak, is achieved. The chip is fabricated in a 1.5-/spl mu/m NMOS production process which utilizes two levels of tungsten interconnect and contains 115000 transistors on an 8.4/spl times/8.4-mm die. A 30-MHz operating frequency is achieved under worst-case operating conditions.