High-speed low-power logic ICs using quasi-normally-off GaAs MESFETs

A digital approach, called `low pinchoff-voltage FET logic' (LPFL), is proposed for high-speed LSI circuit applications. It makes use of `quasi-normally-off' GaAs MESFETs, i.e., Schottky-gate devices operating in enhancement model with a pinchoff-voltage ranging between -0.2 and +0.2 V. Such a V/SUB P/ range is about twice that tolerated by conventional normally-off circuits and thus higher fabrication yields can be routinely achieved. Performances which can be achieved with this approach have been tested by means of a single-clocked frequency divider circuit fabricated with MESFETs of 1 /spl mu/m/spl times/20 /spl mu/m gate geometry.