An opposite side floating gate FLASH memory scalable to 20 nm length

Summary form only given. In this paper, a new opposite side floating gate FLASH memory cell structure based on double-gate MOSFETs is proposed. The new structure decouples the write/erase process with the read process so that a thick gate oxide is used in the write/erase process to preserve non-volatility and a thin gate oxide is used in reading to give a high on/off current ratio in read/standby mode. Simulation results shows that FLASH scaling to the 20 nm node is possible using the new structure.