SPL (super push-pull logic) a bipolar novel low-power high-speed logic circuit

In this contribution we would like to present a new bipolar low -power high -speed logic circuit named SPL (Super Push-pull Logic). At a low POY~~ per gate range of lmw/gate, the calculated path propagation delay time of SPL gates loading wire capacitances of 0.57pF/gate is 2.75 times faster than the one of conventional ECL(Emitter Coupled Logic) gates.