A 6.2 ns 64Kb CMOS RAM with ECL interfaces

Sub-lo ns 64Kb SRAMs with ECL interfaces have been reported in both bipolar and BiCMOS technologies [I-21. This Paper reports the first sub-10 ns 64Kb CMOS RAM with ECL interface signals. The high performance of this RAM is due to the combination of innovative CMOS circuit design and an advanced. selectively scaled CMOS process with 0.5 μm Leff, both of which will be described