A novel self-repairable parallel multiplier architecture, design and test

A novel, self-repairable, parallel multiplier architecture with high speed low power CMOS parallel counter circuits and design-for-test (DFT) implementations is presented. The illustrated 16/spl times/16-b multiplier architecture can be easily reconfigured into 17 different architectures for fault recovering. Also described is a novel verification scheme that performs exhaustive data validation. Compared to previous parallel multiplier architectures, the proposed multiplier architecture has reduced transistor count, enhances yield using built-in self-repair mechanism and provides high performance at low-voltages. The proposed exhaustive DFT technique greatly reduces the test vector length required to verify the data validity, from 17*2/sup 32/ vectors needed in a conventional architecture to only 1.3*2/sup 13/ vectors needed in this architecture. Furthermore, the concepts presented are scalable to larger multiplier architectures.