Simultaneous Clock Wire Sizing and Shield Insertion for Minimizing Routing Blockage

Clock shields are convenient for clock signal integrity, but excessive coupling capacitance that they incur makes it difficult to achieve usual clock design goals such as clock latency and clock skew. Selective shield insertion combined with clock wire sizing is addressed with a goal of minimizing routing blockage, under constraints of maximum clock latency and clock skew. Our approach consists of two components: (1) Message passing neural network (MPNN) model is developed to predict clock arrival time at each clock tree component, e.g. clock buffer, ICG, and flop. (2) Actual clock wire sizing and shield insertion is performed through mixed integer quadratically constrained programming (MIQCP) formulated at each clock tree stage, one by one; this is enabled by the predicted clock arrival time from MPNN. The experiment demonstrates that the predicted clock arrival time from MPNN is close to reference one with R-squared value of 0.954. Clock tree designed with the proposed method indicates the reduction of routing blockage by 38% on average of a few test circuits, compared to state-of-the-art.