Low conversion ratio VRM design

This paper discusses the design considerations for low conversion ratio voltage regulation modules (VRMs) for the next generation of microprocessors, focusing on the handling of large, high-slew-rate current transients. A DC-DC power converter topology which deploys an inductive clamp to handle the unloading transients, while operating at a modest switching frequency, low current ripple and low power dissipation, is discussed. The clamp response is analyzed, and simulation results for a 1 MHz, 100 A, 12-to-1 V VRM are presented.