Design Considerations for Power Delivery Network and Metal-Insulator-Metal Capacitor Integration in Bridge-Chips for 2.5-D Heterogeneous Integration

We investigate design trade-offs in the power de-livery network (PDN) of bridge-chip based 2.5-D heterogeneous platforms. We demonstrate that including the PDN in the bridge-chip can reduce DC- IR drop up to
$\sim$
23 %, lower Ldi/dt noise up to
$\sim$
19 %, and reduce the high-frequency ripple by
$> 3\times$
compared to the baseline case of no PDN in the bridge-chip. We also evaluate the impact of bridge-chip sizing on the on-die maximum transient power supply noise (PSN). 2.5-D designs with both smaller- and larger-width bridge-chips could benefit from decoupling capacitors placed closer to the on-die PDN. We propose the inclusion of these decoupling capacitors within the bridge-chip in the form of metal-insulator-metal (MIM) capacitors and evaluate the trade-off between bridge-chip size and MIM capacitor density. In our CPU and FPGA case study, the maximum transient PSN can be reduced from
$\sim$
19% of VDD to
$\sim$
13.5% of VDD for the CPU (
$\sim$
15% of VDD to
$\sim$
9.1% of VDD for FPGA) by including a PDN and MIM decoupling capacitors in the bridge-chip, with a MIM density of 10 nF/mm
²
and a bridge-chip width of 4.5 mm.