Reconstituted-SiO2 Tier with Integrated Copper Heat Spreader

This work presents a wafer-scale chiplet reconstitution technology for high-density 3D polylithic integration. The key feature of this proposed integration is the use of silicon dioxide deposited by inductive coupled plasma enhanced chemical vapor deposition (ICP-PECVD) and electroplated copper for the encapsulation of multiple chiplets to form a reconstituted-SiO2 tier with an integrated copper heat spreader. Using silicon dioxide as the encapsulant can help achieve high-density and low-loss interconnects and reduce the possibility of misalignments and die-shifts. The electroplated copper on the back of the chiplets improves thermal management. In this paper, a dense array of 150
$\mu \text{mx}150\mu \mathrm{m}$
chiplets that are about 30
$\mu \mathrm{m}$
- thick are partially encapsulated in 15
$\mu \mathrm{m}$
of SiO2 and partially in 36
$\mu \mathrm{m}$
of copper. Preliminary thermal and electrical modeling are carried out to analyze the performance of the proposed reconstituted tier.