A CMOS fractional-N frequency synthesizer for low-power RF applications

A divider-free fractional-N CMOS frequency locked loop synthesizer is presented. The frequency divider used in traditional frequency synthesizers is replaced by a switched-capacitor frequency detector (SC-FD). The architecture of the proposed synthesizer has been successfully simulated at behavioral level to verify its expected functionality. Design considerations of various synthesizer building blocks are discussed to highlight their impact on the synthesizer performance.