A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC

High-speed (GS/s) low-cost ADCs are of increasing interest for wideband communication systems. While technology helps improve the sampling speed of the ADC, the reduced supply voltage and increasingly complex design rules and device modeling impose great challenges on the dynamic range and design cost of high-speed ADC designs. Time-interleaving (T1) SAR ADCs have shown outstanding power efficiency at high speed [1]. However, the limited singlechannel speed leads to massive Tl channels, which inevitably incur excessive overhead in the sampling network and associated clock generation. Time-based ADCs [2–4] provide a solution to high-speed, medium-resolution conversion with considerably reduced Tl channels and circuit complexity thanks to their fast open-loop operation and the significantly reduced inverter delay in advanced technologies. However, it is still challenging and time-consuming to design a tradition high-precision TDC in the presence of thermal noise and device mismatch. Recently, [5] employed stochastic operation [6] in a time-based ADC to exploit those circuit variabilities, demonstrating reasonably decent ADC performance with design automation. However, such a stochastic ADC architecture typically requires an excessively long chain of delay stages to achieve sufficient random samples for final signal reconstruction, resulting in high accumulated noise that limits the achievable ADC resolution.