A Low Noise Bandgap Reference with 0.89 V Vref, 0.88 μVrms noise and 80 dB of PSRR

A low noise, all CMOS voltage reference is proposed and designed for defence applications. The proposed design uses a decoupling capacitor and chopper-stabilization-based-noise-cancellation technique. The design is supported with an extensive process, voltage and temperature (PVT) analysis in a standard 65 nm CMOS technology. The simulation results exhibit 0.89 V of
$\mathbf{v}_{ref}$
with 13.03 ppm/°C temperature sensitivity. The design also shows a spot noise of 3.43 nV at 10 KHz, root mean square (RMS) noise
$(\mathbf{V}_{rms})$
of 1.07
$\mu \mathbf{V}/\sqrt{Hz}$
for 10 Hz to 100 KHz and power supply rejection ratio (PSRR) of 72.83 dB, reported at various worst case PVT corners. At a typical PVT corner, the results show the spot noise of 2.78 nV at 10 KHz,
$\mathbf{V}_{rms}$
noise of 0.88
$\mu \mathbf{V}/\sqrt{Hz}$
for 10 Hz to 100 KHz and the PSRR of 80 dB. The paper also presents the mathematical closed-form noise equations for the proposed circuit. The equations show the mean percentage error (MPE) of 1%, 0.3% and 0.5% for the mean square output noise, the spot noise and the RMS noise respectively.