14.1 A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving −67dBc Fractional Spur

Ring-oscillator (RO)-based injection-locked phase-locked loops (IL-PLLs) and multiplying delay-locked loops (MDLLs) are promising candidates for low-cost, high-performance clock generation, thanks to the largely suppressed phase noise of the RO due to the reference injection, small area, and technology-friendly scaling. For such architectures, the fractional-N operation is typically realized with a digital-to-time converter (DTC) to delay the reference-injection signal with a proper fractional-N phase shift such that it aligns with the RO phase at the injection node. However, the non-idealities of the DTC, including offset, gain, and integral-nonlinearity (INL) errors, introduce a periodic injection error into the RO and are key error mechanisms for generating reference and fractional spurious tones. Previous research on MDLLs or IL-PLLs that addressed DTC non-idealities falls mainly in two categories: DTC error calibration and DTC error randomization. [1], [2] calibrated gain and offset errors, and [3] also corrected INL. However, these techniques are limited by either the error estimation or correction accuracy. [4] demonstrated a nonuniform injection skip to randomize the DTC INL, but the spur reduction is constrained by the limited degree of randomization in addition to the elevated noise floor. To address the aforementioned challenges, we propose 1) an injection-error scrambling technique that allows a higher degree of randomization and thus suppresses spurs even more, 2) a background error compensation technique that mitigates the timing mismatch associated with the injection-error scrambling, and 3) a background third-order delay equalizer that corrects DTC offset, gain, and INL errors at multiple points of an MDLL, with a relaxed analog implementation requirement. For the maximal performance, we performed the DTC error calibration and randomization simultaneously. To prove the concept, a fractional-N digital MDLL prototype was implemented in 65nm CMOS demonstrating
$800\text{fs}_{\text{rms}}$
jitter and −67dBc fractional spur with 29dB spur suppression.