Fault tolerance design of VLSI two dimension systolic processor array

After briefly reviewing the development of the IC, the authors point out the necessity of introducing fault tolerance techniques to IC design. They discuss two fundamental fault tolerance design techniques for two-dimensional systolic array: direct reconfiguration and a fault-stealing algorithm. The authors propose a reconfiguration method which is easier and more successful than that given by M.G. Sami and R. Steffnelli (see Proc. 1984 Real-Time System Symp., IEEE, Austin).<
>