A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures

An AES engine with uniform side-channel-attack (SCA) resistance across time/frequency domains using a high-bandwidth non-linear digital low-dropout (NL-DLDO) regulator in conjunction with AES arithmetic countermeasures is fabricated in 14nm CMOS. Randomized regulator loop parameters and cascading LDO and arithmetic transformations provide >250K× increase in frequency/time-domain MTD, with no CPA attack detected on current/electromagnetic (EM) traces measured from 1 billion encryptions.