A Power-Efficient 24-to-71 GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36dB Inter-Band Blocker Rejection for 5G NR

The coverage of 5G NR frequency range 2 (FR2) keeps scaling towards over 100GHz. Multi-band receivers have been developed to realize reception over multiple 5G FR2 bands with minimized system size [1]–[3]. The conventional multi-band receiver achieves 20-to-44GHz frequency coverage with wide-band RF response and fixed IF [3]. However, facing the fast-scaling 5G FR2 band, the power consumption of such receivers will be increased tremendously due to the enlarged LO frequency coverage. The Hartley receiver architecture has been introduced to decrease the required LO range [1], [2]. Over 30dB Image rejection could also be maintained to provide the inter-band blocker rejection for a dual-band operation. However, the overall system NF is degraded due to amplified noise from the image band and the achievable bandwidth is also limited. This work introduces a 24.25-to-71GHz phased-array receiver. A harmonic-selection technique is proposed to extend the operating bandwidth with low power consumption and over 36dB inter-band blocker tolerance. The proposed phased-array receiver achieves 256-QAM EVMs of −33.3dB, −30.9dB, −31.6dB, and −28.5dB at 28GHz, 39GHz, 47.2GHz, and 60.1GHz, respectively, with the worst-case inter-band blockers. The power consumption for a single receiver channel is 36mW, 32mW, 51mW, and 71mW at 28GHz, 39GHz, 47.2GHz, and 60.1GHz, respectively.