Design of a FinFET based high efficiency RADHARD flip-flop with Transition Completion Detection

Flip-flops plays a vital role in modern microprocessors. Flip-flops, latches, timing elements are demanding for the performance analysis of digital systems due to low power requirement and high timing constraints. In order to point out the completion of transition in sense amplifier stage, sense amplifier flip-flop with transition completion detection (SAFF-TCD) uses internally generated signal. It gates the NMOS transistors in sense amplifier stage and slave latch stages. Self-resetting logic with modified gate diffusion input (SRL-MGDI) based NAND gate is used to scale back power consumption and delay. SRL-MGDI based NAND gate is used to generate internal detection TC signal. Combining the advantages of both SRL and MGDI logic provides tradeoff between speed and power. SAFF-TCD based RADHARD FF with SRL-MGDI NAND gate design, sense amplifier (SA) single event transient propagating to 2 branches in slave latch stage is prevented. Also SA stage cut down the clock loading in the network. Designed flip- flop overcomes operation yield degradation, power consumption, delay and glitches in previous SAFFs. The designs are simulated using FinFET 22 nm Tanner EDA tool with 0.8V supply.