Abstract:
A pipelined noise-shaping successive approximation register (NS-SAR) ADC with 1–2 multistage noise-shaping (MASH) structure is presented. Two-stage pipelined structure co...Show MoreMetadata
Abstract:
A pipelined noise-shaping successive approximation register (NS-SAR) ADC with 1–2 multistage noise-shaping (MASH) structure is presented. Two-stage pipelined structure consisting of 5 bit NS-SAR and 4 bit NS-SAR quantizers enables 3rd-order noise-shaping. A single operational transconductance amplifier (OTA) is shared by an integrator for noise-shaping and a residue amplifier for pipelining to maximize the power efficiency. The measured dynamic range (DR) is 84.6 dB when the sampling rate is 83.3 MS/s, bandwidth is 4 MHz, and power consumption is 3.5 mW showing Schreier figure-of-merit (FoMS,DR) of 175.2 dB. The proposed ADC structure greatly relaxes design requirement of each SAR quantizer and can achieve high resolution and wide bandwidth with good power efficiency.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 56, Issue: 11, November 2021)